`include "defines.svh"

module RISCV_CPU(
    input clk,
    input reset,
    //inst sram
    output        inst_sram_en,
    output word_t inst_sram_addr,
    input  word_t inst_sram_rdata,
    input         axi_inst_flushreq,

    //data sram
    output word_t data_sram_pc,
    output        data_sram_en,
    output        data_sram_wen,
    output logic[3:0] data_sram_mask,
    output word_t data_sram_addr,
    output word_t data_sram_wdata,
    input  word_t data_sram_rdata,
    input         axi_data_flushreq
);


// outports wire
wire   	if_valid;
if_to_id_bus_t   	if_to_id_bus;

IF_STAGE if_stage(
	.clk                 	( clk                  ),
	.reset               	( reset                ),
	.if_valid            	( if_valid             ),
	.id_ready            	( id_ready             ),
	.if_to_id_bus        	( if_to_id_bus         ),
	.id_to_if_bypass     	( id_to_if_bypass      ),
	.exe_to_front_bypass 	( exe_to_front_bypass  ),
	.inst_sram_en        	( inst_sram_en         ),
	.inst_sram_addr      	( inst_sram_addr       ),
    .axi_inst_flushreq 	    ( axi_inst_flushreq    )
);

// outports wire
wire   	id_ready;
wire   	id_valid;
id_to_exe_bus_t   	id_to_exe_bus;
id_to_if_bypass_t   	id_to_if_bypass;

ID_STAGE id_stage(
	.clk                 	( clk                  ),
	.reset               	( reset                ),
	.if_valid            	( if_valid             ),
	.id_ready            	( id_ready             ),
	.id_valid            	( id_valid             ),
	.exe_ready           	( exe_ready            ),
	.if_to_id_bus        	( if_to_id_bus         ),
	.id_to_exe_bus       	( id_to_exe_bus        ),
	.wb_to_id_bus        	( wb_to_id_bus         ),
	.mem_to_id_bypass    	( mem_to_id_bypass     ),
	.id_to_if_bypass     	( id_to_if_bypass      ),
    .exe_to_id_bypass 	    ( exe_to_id_bypass     ),
	.exe_to_front_bypass 	( exe_to_front_bypass  ),
	.wb_to_front_bypass  	( wb_to_front_bypass   ),
	.inst_sram_rdata     	( inst_sram_rdata      ),
    .axi_inst_flushreq 	( axi_inst_flushreq )
);

// outports wire
wire   	exe_ready;
wire   	exe_valid;
exe_to_mem_bus_t   	exe_to_mem_bus;
exe_to_id_bypass_t   	exe_to_id_bypass;
exe_to_front_bypass_t   	exe_to_front_bypass;

EXE_STAGE exe_stage(
	.clk                 	( clk                  ),
	.reset               	( reset                ),
	.id_valid            	( id_valid             ),
	.exe_ready           	( exe_ready            ),
	.exe_valid           	( exe_valid            ),
	.mem_ready           	( mem_ready            ),
	.id_to_exe_bus       	( id_to_exe_bus        ),
	.exe_to_mem_bus      	( exe_to_mem_bus       ),
	.exe_to_id_bypass    	( exe_to_id_bypass     ),
	.exe_to_front_bypass 	( exe_to_front_bypass  ),
	.wb_to_front_bypass  	( wb_to_front_bypass   ),
	.data_sram_pc       	( data_sram_pc        ),
	.data_sram_en       	( data_sram_en        ),
	.data_sram_addr     	( data_sram_addr      ),
	.data_sram_wen      	( data_sram_wen       ),
	.data_sram_mask     	( data_sram_mask      ),
	.data_sram_wdata    	( data_sram_wdata     ),
    .axi_data_flushreq 	    ( axi_data_flushreq  )
);

// outports wire
wire       	mem_ready;
wire       	mem_valid;
mem_to_wb_bus_t       	mem_to_wb_bus;
mem_to_id_bypass_t       	mem_to_id_bypass;

MEM_STAGE mem_stage(
	.clk                	( clk                 ),
	.reset              	( reset               ),
	.exe_valid          	( exe_valid           ),
	.mem_ready          	( mem_ready           ),
	.mem_valid          	( mem_valid           ),
	.wb_ready           	( wb_ready            ),
	.exe_to_mem_bus     	( exe_to_mem_bus      ),
	.mem_to_wb_bus      	( mem_to_wb_bus       ),
	.data_sram_rdata    	( data_sram_rdata     ),
	.mem_to_id_bypass   	( mem_to_id_bypass    ),
	.wb_to_front_bypass 	( wb_to_front_bypass  ),
    .axi_data_flushreq 	    ( axi_data_flushreq   )
);

// outports wire
wire   	wb_ready;
wb_to_id_bus_t   	wb_to_id_bus;
wb_to_dpic_bus_t   	wb_to_dpic_bus;
wb_to_front_bypass_t   	wb_to_front_bypass;

WB_STAGE wb_stage(
	.clk                	( clk                 ),
	.reset              	( reset               ),
	.mem_valid          	( mem_valid           ),
	.wb_ready           	( wb_ready            ),
	.mem_to_wb_bus      	( mem_to_wb_bus       ),
	.wb_to_id_bus       	( wb_to_id_bus        ),
	.wb_to_dpic_bus     	( wb_to_dpic_bus      ),
	.wb_to_front_bypass 	( wb_to_front_bypass  )
);

DPIC_STAGE dpic_stage(
	.clk            	( clk             ),
	.reset          	( reset           ),
	.wb_to_id_bus   	( wb_to_id_bus    ),
	.wb_to_dpic_bus 	( wb_to_dpic_bus  )
);






endmodule
